[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 1;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = clk_in_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_0_LOADNUM = 236;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 6;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = n857;
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_0_LOADNUM = 13;
GLOBAL_SECONDARY_0_SIGTYPE = RST;
; Global secondary clock #1
GLOBAL_SECONDARY_1_SIGNALNAME = cnt_31__N_88;
GLOBAL_SECONDARY_1_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_1_LOADNUM = 18;
GLOBAL_SECONDARY_1_SIGTYPE = CE+RST;
; Global secondary clock #2
GLOBAL_SECONDARY_2_SIGNALNAME = mcu/out_port_7__N_232;
GLOBAL_SECONDARY_2_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_2_LOADNUM = 10;
GLOBAL_SECONDARY_2_SIGTYPE = CLK+RST;
; Global secondary clock #3
GLOBAL_SECONDARY_3_SIGNALNAME = mcu/port_id_7__N_215;
GLOBAL_SECONDARY_3_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_3_LOADNUM = 8;
GLOBAL_SECONDARY_3_SIGTYPE = CLK+RST;
; Global secondary clock #4
GLOBAL_SECONDARY_4_SIGNALNAME = mcu/clk_in_c_enable_175;
GLOBAL_SECONDARY_4_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_4_LOADNUM = 13;
GLOBAL_SECONDARY_4_SIGTYPE = CE;
; Global secondary clock #5
GLOBAL_SECONDARY_5_SIGNALNAME = mcu/n10021;
GLOBAL_SECONDARY_5_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_5_LOADNUM = 12;
GLOBAL_SECONDARY_5_SIGTYPE = RST;
; I/O Bank 0 Usage
BANK_0_USED = 9;
BANK_0_AVAIL = 26;
BANK_0_VCCIO = 3.3V;
BANK_0_VREF1 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 7;
BANK_1_AVAIL = 26;
BANK_1_VCCIO = 3.3V;
BANK_1_VREF1 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 12;
BANK_2_AVAIL = 28;
BANK_2_VCCIO = 3.3V;
BANK_2_VREF1 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 2;
BANK_3_AVAIL = 7;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;
; I/O Bank 4 Usage
BANK_4_USED = 4;
BANK_4_AVAIL = 8;
BANK_4_VCCIO = 3.3V;
BANK_4_VREF1 = NA;
; I/O Bank 5 Usage
BANK_5_USED = 4;
BANK_5_AVAIL = 10;
BANK_5_VCCIO = 3.3V;
BANK_5_VREF1 = NA;
